Projeto de um ADC SAR assíncrono de 10 bits com chaveamento monotônico em tecnologia CMOS de 180 nm para aplicações biomédicas

Abstract

In recent years, it is possible to observe a quickly adoption and daily use of wearable electronic devices such as watches and smart bracelets. Such devices have dedicated systems for monitoring biological signals, such as heartbeat and blood oxidation, and some of these devices already have the ability to provide measurements of electrocardiogram (ECG) and blood pressure signals. Additionally, these devices also feature wireless connection via Bluetooth or Wi-Fi communication protocols. Both modern instrumentation and communication systems require the digitization of analog signals for further digital signal processing. Analog-to-tal converters (ADCs) are electronic circuits that digitize analog signals, and are present in different electronic devices. This work presents the design of a Successive Approximation Register (SAR) ADC for low voltage applications with 10 bits and 5 kSPS asynchronous. The ADC is designed in 180 nm CMOS technology and operates at a nominal voltage of 0.5 V. The electrical schematic level simulations indicate that the ADC reached a signal-to-noise-to-distortion (SNDR) ratio of 61.36 dB, leading to an effective number of bits (ENOB) of 9.90 bits. The spurious-free dynamic range (SFDR) is 73.19 dB, and the total power consumption of the ADC is 1.43 μW. Keywords: Analog-to-Digital Converter, Successive Approximation Register, Low Voltage, Low Power, Integrated circuits, Analog Design.