Modelagem comportamental e elétrica de um modulador sigma-delta em tempo contínuo de baixa tensão para a faixa de áudio

Abstract

The migration of signal processing to the digital domain allows for more reliable and efficient results compared to continuous domain signal processing. Digital circuits have been commonly improved, making their circuits increasingly complex, accurate, and fast. However, as the nature of audio signals is analog, there is a need to use high-resolution analog-to-digital converters (ADCs) for an audio acquisition with a high signal-to-noise ratio (SNR), capable of transforming analog information in digital words so that the digital processing cores can process the information with greater performance. This master’s dissertation presents a behavioral and electrical modeling of a continuous-time sigma-delta modulator (CT-SDM) for the audio range capable of operating at low voltage. The behavioral model of 2 CT-SDMs with different feedback digital-to-analog converter (DAC) topologies is developed. The first is a CT-SDM with a 1-bit non-return-to-zero (NRZ) DAC implemented with a CMOS inverter and the second uses a finite impulse response (FIR) filter of 6 taps as feedback DAC. The latter proved to be the best choice as it presented a reduction in the area and power consumption of the first integrating stage. A methodology based on circuits programmed in VerilogA is used to estimate the minimum requirements of the operational amplifier used in the first integrator, which has a greater impact on the performance of the CT-SDM. Finally, the electrical design of the CT-SDM is presented using a 6-tap FIR type DAC in 0.18 μm CMOS technology and 0.5 V supply voltage. The CT-SDM was simulated using circuits designed at the transistor level and keeping the 2nd and 3rd integrators with ideal amplifier models programmed in VerilogA. The results of conservative transient simulations without and with noise resulted in a signal-to-noise-and-distortion ratio (SNDR) and effective mumber of bits (ENOB) of 95.71 dB/15.60 bits and 82.28 dB/13.37bits, respectively. This CT-SDM presented a power consumption of 40.02 μW, resulting in a Walden Figure of Merit (FoM) of 94.50 fj/conv., without considering the power of the 2nd and 3rd integrators. Keywords: Sigma-Delta Modulation, Analog-to-Digital Converter, Audio Signals, Low Voltage.