Análise de desempenho de aplicações eBPF/XDP em planos de dados programáveis

Abstract

The Extended Berkeley Packet Filter (eBPF) is a subsystem of Operating System Core (kernel) that filters network packets on data plane devices with the aid of Hook eXpress Data Pat (XDP). Hook XDP allows programs eBPF to process network packets in user space, kernel space, in the card drivers and also in the card hardware of network. Despite efforts to evaluate the performance of eBPF programs, existing analyzes still do not evaluate the execution of different programs eBPF processing different packet sizes for all existing approaches to Hook XDP. This work aims to analyze the capabilities and limitations that eBPF programs reach by processing packets in different approaches to Hook XDP with SmartNICs. Therefore, we perform performance evaluations such as Latency, Transfer Rate and CPU usage for the execution of various programs eBPF on SmartNICs with support for all Hooks XDP. In our work, we studied the Software-Defined Network (SDN) paradigm and the programmable data plane with eBPF/XDP. Then, we carried out a survey of the main works related to eBPF/XDP and presented the methodology used to carry out the experiments and evaluations. Our results showed that the XDP Generic and Native modes were able to maintain the SmartNIC’s maximum Throughput when processing large packets with algorithms of up to 3200 memory accesses. The AF_XDP mode also achieved good transfer rates when processing large packets, but only for algorithms with up to 100 memory accesses. The XDP Generic mode manages to maintain minimal latency when processing packets with up to 1600 memory accesses.The XDP Native and AF_XDP modes can perform up to 3200 memory accesses with low latency. When evaluating the CPU usage, we noticed that when processing millions of small packets, the cores usage is always at 100% due to the millions of interrupts generated by the CPU. When we increase the size of each packet, the total amount of packets decreases considerably, showing that the percentage of usage of all cores decreases due to the large decrease in interrupts generated by the CPU. In the evaluations of the number of instructions, number of branches, number of load hits and load misses, the results showed that there were no differences in behavior between the different experiments.