Ferramenta web semiautomática para geração de ambientes de verificação UVM com SystemVerilog

Abstract

Currently, the insertion time of a hardware pro ducts in the market is decreasing despite the growth of its complexity. Therefore, it is important that the construction process is getting faster and faster. Among the ways to gain performance, the optimization of the time spent in verification is fundamental, because ab out 70% of the project time is applied in this activity. This process starts with the development, because if an error is detected only in the final stage of development, there may be delays to comply with delivery times. In this way, this work presents USAG, a semi-automatic tool developed to construct verification environments using the UVM methodology (which is the current standard methodology) applied to the design of integrated circuits written in SystemVerilog. This tool comes to assist in the hardware verification process by accelerating the creation of the verification environment as it generates the structures and interconnections of the methodology and produces the files for simulation. Any tool that supports SystemVerilog together with the UVM Methodology can execute the verification environment generated by the USAG. In addition, the tool is web-based to be accessible from any lo cation without the need for a specific operating system or configuration to use it. Finally, the results of UVM verification environments obtained from the entry of source co des in SystemVerilog in USAG are presented.