Projeto de um Controlador de DMA de Alta Vazão para Transferência de Dados

Abstract

This work aims to develop a DMA (Direct Memory Access) controller in VHDL (VHSIC Hardware Description Language) language with focus on high data throughput. The DMA is subsequently integrated into a system consisting of a parameterized RAM (Random-access Memory) memory controller, with feature of data interleaving, and an I/O (In/Out Data) device controller which are also developed by author in VHDL language. The project is developed using Altera Quartus II and Altera ModelSim softwares. A DMA controller performs data transfers between memory controller and I/O device is obtained as final result of this work.