Arquitetura de uma unidade aritmética em ponto flutuante padrão IEEE754 32 bits

Abstract

Floating point arithmetic is used for numerous applications requiring a high data together with a great precision, such as voice and image processing. The hardware responsible for floating point arithmetic is called FPU (Floating Point Unit). The FPU can be used both as a co-processor in a system or embedded on a more complex processor for a specific application. Typically, these units are designed to follow a standard for floating point arithmetic. The IEEE754 standard, which provides guidelines for representing floating point numbers, is adopted in order to standardize and match hardware from different manufacturers. This paper presents a proposed architecture for floating point arithmetic in the IEEE 754 Standard in register transfer level (RTL) for implementation in FPGA. The proposed FPU uses single precision and is able to perform operations such as addition, subtraction, multiplication and division. By means of the methodology adopted by the Brazil-IP program, several steps are realized aimed the development an IP-core with cost and quality desired. The FPU is intended for applications where the requirement of area is limited, as embedded systems and integrated systems on a chip (SoC). The results are validated by comparing topologies of existing open source FPUs.