Desenvolvimento de arquiteturas digitais para o módulo de transformadas, segundo o padrão HEVC de codificação de vídeo

Abstract

There has been an increasing demand for higher quality video, considering the high amount of electronic devices that process digital video, resulting in increasingly high resolutions. For that purpose, video coding techniques are used, which have as main goal the reduction of the required representation to process a digital video, implying in no loss of the visual quality of the transmitted and stored video. This work proposes a 1-D architecture Transform module (Discrete Cosine Transform) of the H.265 (HEVC) digital video encoder. Furthermore, the proposed work implements a digital hardware structure able to process all the four sizes (4x4, 8x8, 16x16 and 32x32) of residual matrixes, by using a purely combinational fashion. As result, energetic efficiency is achieved by inserting a low-power technique, based on a statistical analysis of the use of these transforms when playing real videos segments, without significant prejudice to the architecture performance. The functional validation was made using Mentor Graphics software Modelsim, and the frequency, area and power consumption results were obtained for ASIC 65 nm ST gate library synthesis, using Cadence RTL Compiler tool.