Desenvolvimento de uma Arquitetura em Hardware do Bloco de Binarização do CABAC Baseado no Padrão HEVC

Abstract

The entropy encoder is responsible for the symbolic data representation in order to represent it with a smaller number of bits. In HEVC standard, there is only one type of entropy coder, the CABAC (Context Adaptive Binary Arithmetic Coding), which is similar to that used in the previous standard, H.264/AVC, but it has been modified to facilitate the parallel processing. This work presents a hardware architecture for the binarization block of CABAC, which is the first block in the entropy encoding process. This block aims to reduce the alphabet symbols size, thus simplifying the costs of context modeling and facilitating the task of the arithmetic coding. As a result of this work, an architecture with efficient performance and reduced power consumption was sought. The synthesis of architecture was performed by using, the RTL Compiler from Cadence tool and 65 nm ST gates library. The results show that synthesis of the final proposed architecture has reached a reduction in power consumption up to 41% compared to the initial architecture.