Implementação e validação de uma arquitetura em hardware do interpolador para o bloco de compensação de movimento baseado no padrão HEVC

Abstract

The large increase in devices with high resolutions also grows the demand for video quality that, in turn, increases the video traffic over the Internet and other forms of communication. Thus, it is necessary to encode video in order to eliminate redundant information in video sequences. The task of coding has a high degree of complexity, which prevents its performance purely in software to serve users with videos that have frame rates enough, so that there is latency-at-game (LAGs), namely the display time interval between frames, which is large enough for the user to feel the sense of crashes. Battery is the main bottleneck of the current mobile embedded technology, which implies it should be used efficiently. Therefore, hardware solutions come as contour possibilities at this mentioned context. This work proposes a hardware implementation of interpolating block within the motion compensation context based on the standard video encoding HEVC to achieve gains in performance and reduced power consumption.