Filtros reconfiguráveis em tecnologia CMOS para circuitos receptores de RF Multi-Padrão

Abstract

This work presents the design of two reconfigurable Gm-C low-pass filters for multi-standard zero-IF receivers developed in a 180 nm CMOS process with 1.8 V power supply. The first one is composed by a series of parallel OTAs (Operational Transconductance Amplifiers) activated or deactivated by two control bits to achieve bandwidth exibility. Four operation modes are possible with this arrange. Post-layout simulations indicate that the designed filter achieves cutoff frequencies of 2.54/5.11/7.68/10.29 MHz with power consumption between 10.27 to 12.29 mW. However, the circuit achieved low linearity (IIP3 < 4 dBm) and the power scalability was negatively affected due to the high power consumption of the common-mode control circuit (CMFB). This digitally reconfigurable filter was prototyped and measured. The second filter was designed aiming the improvement of linearity and reduction of power consumption. Thus, a transconductor was implemented as the basic cell using some linearization techniques: source degeneration, pseudo-differential pair and double differential pair. Triode-region transistors were employed as current sources to replace the degenerated resistors and to provide continuous control of cutoff frequencies by changing the voltage applied on it's gates. Schematic simulations indicate that this continuous reconfigurable filter works with cutoff frequencies in the range of 2.5 to 10 MHz, consuming 5.83 to 9.04 mW. Linearity improvement was achieved: the minimum and maximum IIP3 was 4.72 dBm and 17.2 dBm, respectively. In the other hand, the use of a double dfferential pair resulted in the increase of filter's noise. Nevertheless, both designed filters presented a similar performance when compared to recent related works available in the literature. The designed filters can be applied in receivers of mobile communication systems like WCMDA, HSPA, LTE and WiMAX.