Otimização de área e dissipação de potência em arquiteturas da transformada rápida de Fourier utilizando multiplicação de constantes múltiplas

Abstract

Digital implementations of the Fast Fourier Transform (FFT) are widely used in communication systems using Orthogonal frequency-division multiplexing. These systems currently comprise several communication standards such as: IEEE 802.11agjn, IEEE 802.20 mobile wireless broadband access, asymmetric digital subscriber lines and digital audio and video broadcasting. Thus, this work proposes a methodology using a multiple constant multiplication (MCM) solution to optimize single stage, radix-2 decimation-in-time FFT processors. It uses the algorithm proposed by Cooley and Tukey to determine the coefficients of the FFT and the algorithm proposed by Aksoy et. al to solve the MCM problem. Also, is developed an algorithm that automatically elaborates the FFT architectueres using the hardware description language SystemVerilog. Each architecture is functionally verified and logically synthesized utilizing XFAB 0.18𝜇𝑚cells library. The usage of this methodology aims to optimize results in area and power comsumption in architectures from 8 up to 256 points.