Uma ferramenta de auxílio ao projeto de circuitos integrados analógicos integrada ao ambiente cadence virtuoso

Abstract

This work presents a CMOS transistor sizing tool based on biasing and electrical simulation, integrated in the Cadence Virtuoso ®design environment, using the Python and Cadence SKILL programming languages, and the Cadence Spectre® electrical simulator. Aiming to aid analog integrated circuits projects, the sizing tool has a customizable project flow using basic functions, and it is compatible with the TSMC 180 nm and 65 nm technology. It is described the methodology used in the development of this tool, and as results, it is shown the application of the developed software in the project of four basic analog integrated circuit topologies. Keywords: Microelectronics. Transistor sizing tool. Python. Analog integrated circuits, Cadence SKILL.