Projeto de um ADC flash de 3 bits do tipo rail-to-rail completamente diferencial para aplicações de baixa tensão

Abstract

Low-voltage and low-power integrated circuits are being used more by the electronic industry. The reduction of the power supply voltage impacts the excursion of input and output signals. Thus, the development of electronics circuits with rail-to-rail input capability is desired. Analog-to-digital converters (ADCs) are key blocks in many devices, from low-frequency signal acquisition applications to the quantization in low-IF and zero-IF receivers. This work presents the design of Flash ADCs for low-voltage applications. To design a Flash ADC it is necessary to design a resistive voltage divider ladder, comparators, and a binary-to-thermometer decoder. This work is divided em two parts: initially, prototype 01 is presented. It is powered by a 0.6-V power supply and is composed of single-ended comparators and a Wallace-Tree decoder. The second part of this work presents prototype 02, which works for a 0.5-V power supply and is composed of fully-differential comparators and a mux-based decoder. The Flash ADCs designed in this work have rail-to-rail input capability and the simulation results of both ADCs are presented. Two CMOS comparator topologies are used in the ADCs to allow low-voltage operation: A Double-Tail comparator with NMOS input pair transistors and a Dynamic-Latch comparator with PMOS input pair. The circuits are designed in a 180-nm CMOS process with a sampling frequency of 38,192 MHz in prototype 01 and 20 MHz in prototype 02. The power consumption of prototype 01 is 19.97 μW while the total power consumption of prototype 02 is 60.6 μW at schematic-level simulations and 67.75μW at post-layout simulations. Keywords: Analog-to-digital Converters, Flash ADC, Low Voltage, Low Power, Analog Design, Layout Design, Double-tail comparator, Dynamic-latch comparator, mux-based-decoder, Wallace-tree-decoder.