Projeto de uma unidade lógica aritmética

Abstract

This work implements an 8 bits Arithmetic Logic Unit (ALU) using bit-slice structure from the through chip level physical design using CMOS technology. Two types of logical mappings models will be compared in terms of circuit area and number of transistors. Concern about the area is related to the manufacturing cost of the circuit and the number of circuits that can be manufactured on a single silicon wafer. Additionally to this, the number of transistors affects the power drain. This kind of concern is of particular interest in projects of portable devices that operate with batteries. The mapping of logical circuits is one aspect that has great impact on the structure of the circuit. In this project, the initial implementation of the ALU was performed using mapping for NAND gates. From the design specification for one slice, we obtained the initial logic equations, which were minimized, factored and decomposed. Following was done the mapping using NAND gates and then performed the design of the circuit layout using MARTELO software. In the second step was the mapping of circuit for complex gates, getting the layout of the circuit using ASTRAN software. In the process of obtaining the physical circuit, optimizations in number of transistors were done in several levels of project’s workflow.