Especulando a arquitetura do processador MIPS para filtros FIR

Abstract

This work provides a speculation of MIPS processor architecture using a VHDL description. The speculation has as target a DSP filter algorithm, more specifically, a FIR filter applied to frequency attenuation of the human voice in a song. To perform such speculation, an implementation in VHDL of a minimalist MIPS pipeline organization is adopted, corresponding to a small subset of instructions supported without coprocessors, obtained from a hardware design repository site. From the minimalist design reference and the study of the application, complementary hardware support is included for other key instructions required for the application. Besides the instruction set speculation itself, this work focus also on evaluation of alternatives that fill the lack of a floating point coprocessor, in the perspective that the target application needs to operate on the set of real numbers and that the MIPS processors usually adopts floating point operations to execute such kind of work. In particular, at first, is checked the applicability of floating point emulation conversion to fixedpoint arithmetic, based on a comparison of ALUTs consumption versus performance. In a second phase, software is developed for uploading data to processor's memory already in the fixed-point format. Moreover, ISA is extended with a new instruction to optimize processor performance regarding the target voice suppression application. In addition, a methodology is proposed and evaluated to validate the efficiency of the filter algorithm applied to voice suppression in a given music and a set of basic experiments to demonstrate the correctness of the FPGA synthesis of the speculated MIPS architecture.