Investigando paradigmas de programação paralela sobre o MPSoC HeMPS

Abstract

A Multiprocessor System on the Chip MPSoC is a system composed of several processing elements PEs. It is a technology that allows the execution of multiple tasks in parallel, such as multicore computers. However, unlike those computers with few cores, a MPSoC tends to have hundreds of PEs. Generally the communication between the PEs of na MPSoC is implemented via messages, which are transmitted through the channels of na Intra-Chip Network (NoC). Due to the structural similarity, it is believed that the same models used in the programming of parallel machines (clusters and Graphics Processing Units (GPUs)) can be used in MPSoCs. Among them, we can mention: Master-Slave; Pipeline; Parallel Phases; and Divide and Conquer. In this context, the present work aims to investigate the use of parallel programming paradigms in the development of applications for MPSoCs. For this purpose, Matrix Multiplication, AES, and Image Manipulation applications were implemented in the Master-Slave, Pipeline and Divide and Conquer paradigms. In addition, a tool, called HeMPS Parallel Programming, was proposed with the objective of assisting the programmer in the parallelization of applications. Two criteria were considered for the comparison between the paradigms: execution time and consumption of energized processors. The results obtained allowed to conclude that Pipeline was the paradigm that presented better performance and lower power consumption for the Image Manipulation application. However, their results were worse than those obtained by the sequential version. Thus, not justifying the adoption of parallelism for the size of simulated images. Already the Master-Slave paradigm presented better performance and lower energy consumption for the Matrix Multiplication and AES applications for the simulated input domains. However, the Divide and Conquer paradigm tends to have better run-time results for Matrix Multiplication and AES applications when the input size increases.